1. Field of the Invention
The present invention generally relates to a digital signal processor (DSP), and more particularly to a boot (download) process in a device having a plurality of DSPs. Further, the present invention is concerned with a switch system having the function of encoding and decoding voice by using DSPs.
The DSP is capable of processing a large amount of data efficiently and is thus applied to various electronic devices. For example, the DSP is used, in the mobile telecommunications, to form a codec (coder and decoder) for voice encoding and decoding in switch systems.
2. Description of the Related Art
FIG. 1 is a block diagram of a mobile telecommunication system, which includes a plurality of switch stations, radio stations, portable terminals and telephone terminals. Each of the switch systems is equipped with a codec processing part which encodes and decodes voice signals.
The switch stations are connected to a large number of terminals and radio stations. Thus, the codec processing part in each switch station is required to have a sufficient number of channels and perform the voice encoding and decoding at a high speed. Generally, the codec processing part is made up of a plurality of DSPs equal in number to the channels. A boot type (download type) DSPs are mainly used in order to cope with a fault in a codec process algorithm and upgrading thereof.
FIG. 2 shows a structure of the codec processing part. The codec processing part includes a plurality of units equal in number of channels, and the respective units include master ROMs 101, 102 and 103, and DSPs 111, 112 and 113. The DSPs 11, 112 and 113 are connected to peripheral circuits 121, 122 and 123, respectively. When a call request occurs in a channel (it will now be assumed that the peripheral circuit 121 receives such a request), the peripheral circuit 121 sends a boot (download) permission signal to the DSP 111. Upon receipt of the boot permission signal, the DSP 111 sends an address (boot address) to the master ROM 101. Then, data stored in a memory area of the master ROM 101 specified by the address is read and supplied (downloaded) to the DSP 111. When the data is completely downloaded to the DSP 111, the DSP sends a boot complete signal to the peripheral circuit 121. Then, the peripheral circuit 121 makes a connection of the call, and the DSP 111 starts the codec process. When there is no call request, the boot process is not executed.
Nowadays, the number of mobile terminals is increased and the number of switch stations is thus increased. Further, in terms of efficient use of communication channels, it is frequently required to modify the codec process algorithm such as upgrading thereof and provide various maintenance services for coping with faults or the like. As described previously, the codec processing part has the units equal in number to the channels, and in other words has master ROMs and DSPs equal in number to the channels. Hence, it is required to independently handle the master ROMs equal in number to the channels in order to modify the programs of the algorithm stored therein. The above word is troublesome.
Generally, the user requests the codec processing part to continue to stably operate during tens years. After the switch station is shipped to and installed in the user, it is very difficult to do a repair work of the codec processing part. Further, during the repair work, the terminal users cannot use the portable terminals. Hence, it is desirable that the codec processing part continues to stably operate semipermanently. However, in practice, a fault occurs in the codec processing part. For example, there a comparatively high possibility that the contents of memories such as master ROMs may be damaged due to an unexpected variation in the power supply. Hence, it is the important issue to cope with damage to the memories. However, if means for coping with damage to the memories is excessively provided, it may take a very long time to receive a call and make a connection for the call. This will be inconvenient to the terminal users. That is, it is very important to cope with damage while the users can be kept comfortable. Further, even if this is realized, it is necessary to avoid an excessive increase in the amount of power consumed.
It is an object of the present invention to provide a device having a plurality of DSPs in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a device equipped with a plurality of DSPs which is substantially immune to damage to memories.
A further object of the present invention is to provide a device equipped with a plurality of DSPs which can consume a reduced power and avoid degradation of services to users.
The above objects of the present invention are achieved by a device comprising: a plurality of DSPs; instruction memories respectively provided to the DSPs; a master memory storing download information which is to be written into the instruction memories; and an address generator generating addresses of the instruction memories and the master memories.
The above device may be configured so that the DSPs which are in an idle state periodically receive the download information from the corresponding instruction memories.
The device may be configured so that one of the DSPs which are in an idle state receives the download information from a corresponding one of the instruction memories at one time so that the DSPs which are in the idle state sequentially receive the download information at respective different timings.
The device may be configured so that, when a process request occurs, one of the DSPs which has most recently received the download information accepts the process request.
The device may be configured so that each of the DSPs receives the download information from a respective one of the instruction memories in accordance with a state of a given signal externally supplied to the device.
The device may be configured so that: when a first DSP which is one of the DSPs is receiving the download information from a first corresponding one of the instruction memories, a second DSP which is another one of the DSPs starts to receive the download information from a second corresponding one of the instruction memories in accordance with an address value identical to that for the first DSP; and when the first DSP receives all of the download information, the second DSP continues to receive the rest of the download information from the second corresponding one of the instruction memories.
The device may be configured so that the address generator generates the addresses so that values of the addresses change circularly.
The device may be configured so that: the download information contains pieces of data respectively assigned labels; when a first DSP which is one of the DSPs is receiving the download information from a first corresponding one of the instruction memories, a second DSP which is another one of the DSPs starts to receive the download information from a second corresponding one of the instruction memories so that the second DSP receives the piece of data of the download information having the same label as that assigned to the piece of data of the download information which the first DSP receives; and when the first DSP receives all of the download information, the second DSP continues to receive the rest of pieces of data forming the download information from the second corresponding one of the instruction memories.
The device may be configured so that: the download information contains pieces of data respectively assigned labels; the DSPs which are in an idle state simultaneously start to receive the download information from the corresponding instruction memories so that the DSPs simultaneously receive pieces of data having the same label.
The device may be configured so that one of the DSPs which are receiving the download information receives a process request, the above one of the DSPs accepts the process request after all the pieces of data of the download information are received.
The device may be configured so that the DSPs perform a voice encoding and decoding process.
Another object of the present invention is to provide a switch device having a function of a voice encoding and decoding process, the switch device comprising: a plurality of DSPs; instruction memories respectively provided to the DSPs; a master memory storing download information which is to be written into the instruction memories; and an address generator generating addresses of the instruction memories and the master memories.